In storage systems such as optical and magnetic storage systems, as well as in some communication systems, user data are usually first encoded by an outer Error Correcting Code (ECC), then encoded by a modulation encoder, and finally optionally encoded by an inner channel encoder. The modulation encoder could be of the Run Length Limiting (RLL) type, the Running Digital Sum limiting (RDS) type or the Direct Current Free (DCF) type. The output of the modulation encoder (or the inner channel encoder if used) can be pre-coded before being recorded onto the media and read by the detector. On the detection side, a Viterbi algorithm is usually used to reconstruct the coded bits. The primary task of the modulation code is to facilitate the front-end stages of the channel, such as a preamp, a timing circuit, an equalizer and others. At the same time, the modulation encoder modifies the distance properties of the output code words of the channel, and therefore can also improve the Bit Error Rate (BER) and Sector Failure Rate (SFR) characteristics of the system.
The conventional modulation codes described in the literature usually employ a state transition diagram. In a finite state encoder, arbitrary user data are encoded to a constraint data sequence via a finite-state machine. The encoder is said to have rate m/n if at each step of the encoding process, one m-tuple of user data is encoded to one n-tuple of constraint data in such a way that the concatenation of the encoded n-tuples obeys the given constraint. The finite-state machine has multiple states, and the encoder or decoder moves from one state to another after the generation of each output tuple. A single error in the received sequence can trigger the generation of wrong states in the decoder, and in result produce a long sequence of errors. This phenomenon is called “error propagation”, and is often related to the modulation codes constructed from finite-state machines. For the purpose of limiting error propagation, decoding can be implemented via a sliding-block decoder. The state-splitting algorithm can be used for designing the finite state encoders for small and moderate values of n, but for large values of n, it usually requires the use of large tables assigning data to codewords in the encoding graph, and is not feasible from a practical point of view.
Recently, various types of iterative detection schemes based on turbo codes, low density parity check (LDPC) codes and turbo product codes (TPC) were developed for application in storage and communication systems. They provide very low BER, but usually require the use of an interleaver after the modulation encoder. An interleaver changes the order of the already coded bits, and in result nullifies the operation of the modulation encoder. Since encoders based on finite state machines transform the data bits using mapping tables without special structure, the use of such codes in channels with interleaving coded bits is impossible or severely restricted, especially, when they are applied for the encoding parity bits of the TPC or LDPC codes.
Embodiments of the present invention provide solutions to these and/or other problems, and offer other advantages over the prior art.